Predictive Technology Model (PTM)

This site hosts predictive transistor model files developed in the PTM project. PTM evolved from the earlier Berkeley Predictive Technology Model by the Device Group, University of California, Berkerley. From 2005 to 2012, PTM developed models for bulk CMOS and FinFET devices, scaling down to the 7nm node. The project was sponsored by Semiconductor Research Corporation.

FinFET Models

Please start from models and param.inc.

7nm PTM-MG: HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS.
10nm PTM-MG: HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS.
14nm PTM-MG: HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS.
16nm PTM-MG: HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS.
20nm PTM-MG: HP NMOS, HP PMOS, LSTP NMOS, LSTP PMOS.

Bulk CMOS Models

PTM for high-performance (HP) and low-power (LP) applications:

22nm PTM: HP, LP.
32nm PTM: HP, LP.
45nm PTM: HP, LP.

PTM for conventional bulk CMOS devices:

65nm PTM: model.
90nm: model.
130nm: model.
180nm: model.

References

Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011 (http://dx.doi.org/10.1007/978-1-4614-0445-3).
S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, “Exploring sub-20nm FinFET design with predictive technology models,” Design Automation Conference, pp. 283-288, 2012.
W. Zhao, Y. Cao, “New generation of predictive technology model for sub-45nm early design exploration,” IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816-2823, November 2006.
Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, “New paradigm of predictive MOSFET and interconnect modeling for early circuit design,” Custom Integrated Circuits Conference, pp. 201-204, 2000.