Publications

G. Krishnan, S. K. Mandal, C. Chakrabarti, J. Seo, U. Y. Ogras, Y. Cao, “In-memory computing for AI accelerators: Challenges and solutions,” Chapter 2, pp. 199-224, in Embedded Machine Learning for Cyber-Physical, IoT, and Edge Computing, Springer Nature, 2023.

V. Narayanan, Y. Cao, P. Panda, N. R. Challapalle, X. Du, Y. Kim, G. Krishnan, C. Lee, Y. Li, J. Sun, Y. Venkatesha, Z. Wang, “Overview of recent advancements in deep learning and artificial intelligence,” Chapter 2, in Advances in Electromagnetics Empowered by Artificial Intelligence and Deep Learning, IEEE Press and Wiley, pp. 23-80, 2023.

G. Krishnan, S. K. Mandal, A. A. Goksoy, Z. Wang, C. Chakrabarti, J. Seo, U. Y. Ogras, Y. Cao, “End-to-end benchmarking of chiplet-based in-memory computing,” in Neuromorphic Computing, Edited by Y. Yi and H. An, IntechOpen, pp. 1-28, 2023.

A. D. Gaidhane, R. Saligram, W. Chakraborty, S. Datta, A. Raychowdhury, Y. Cao, “Design Exploration of 14nm FinFET for Energy Efficient Cryogenic Computing,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 9, no. 2, pp. 108-115, December 2023.

Z. Zhu, H. Sun, T. Xie, Y. Zhu, G. Dai, L. Xia, D. Niu, X. Chen, X. S. Hu, Y. Cao, Y. Xie, H. Yang, Y. Wang, “MNSIM 2.0: A behavior-level modeling tool for processing-in-memory architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 11, pp. 4112-4125, November 2023. 

A. Moitra, A. Bhattacharjee, R. Kuang, G. Krishnan, Y. Cao, P. Panda, “SpikeSim: An end-to-end compute-in-memory hardware evaluation tool for benchmarking spiking neural networks,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 11,  pp. 3815-3828, November 2023.

J. S. Vetter, P. Date, F. Fahim, S. R. Kulkarni, P. Maksymovych, A. A. Talin, M. G. Tallada, P. Vanna-iampikul, A. R. Young, D. Brooks, Y. Cao. W. G.-Yeon, S. K. Lim, F. Liu, M. Marinella, B. Sumpter, N. R. Miniskar, “Abisko: Microelectronics codesign of spiking neural networks using novel materials,” International Journal of High Performance Computing Applications, vol. 0, pp. 1-29, June 2023.

A. D. Gaidhane, Z. Yang, Y. Cao, “Graph-based compact modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach,” Solid State Electronics, Elsevier, vol. 201, pp. 1-4, March 2023.

H. Suh, J. Meng, T. Nguyen, V. Kumar, Y. Cao, J. Seo, “Algorithm-hardware co-optimization for energy-efficient drone detection and resource-constrained FPGA,” ACM Transactions on Reconfigurable Technology and Systems, vol. 16, no. 2, pp. 1-25, May 2023.

W.-C. Wang, R. Saligram, S. Sharma, M. Lee, A. Gaidhane, Y. Cao, A. Raychowdhury, S. Datta, S. Mukhopadhyay, “Cool-CIM: Cryogenic operation of analog compute-in-memory for improved power-efficiency,” International Electron Devices Meeting, pp. 1-4, 2023.

Z. Wang, J. Sun, A. A. Goksoy, S. K. Mandal, J. Seo, C. Chakrabarti, U. Ogras, V. Chhabria, Y. Cao, “Benchmarking heterogeneous integration with 2.5D/3D interconnect modeling,” International Conference on ASIC, pp. 1-4, 2023.

G. Krishnan, G. R. Nair, J. Oh, A. Anupreetham, P. S. Nalla, A. Hassan, I. Yeo, K. Kasichainula, J. Seo, M. Seok, Y. Cao, “3D-ISC: A 65nm 3D compatible in-sensor computing accelerator with reconfigurable tile architecture for real-time DVS data compression,” Asian Solid-State Circuits Conference, pp. 1-3, 2023.

D.-W. Jee, S.-M. Ko, K. Kasichainula, I. Yeo, Y. Cao, J. Seo, “A time-memory-based CMOS vision sensor with in-pixel temporal derivative computing for multi-mode image processing,” European Solid State Circuits Conference, pp. 109-112, 2023.

F. Zhang, W. He, M. Liehr, I. Yeo, N. Cady, Y. Cao, J. Seo, D. Fan, “A 65nm RRAM compute-in-memory macro for genome sequencing alignment,” European Solid State Circuits Conference, pp. 117-120, 2023.

Z. Wang, P. S. Nalla, G. Krishnan, R. V. Joshi, N. C. Cady, D. Fan, J. Seo, Y. Cao, “Digital-assisted analog in-memory computing with RRAM devices,” International VLSI Symposium on Technology, Systems and Applications, pp. 1-4, 2023.

T. Zhang, K. Kasichainula, D. Jee, I. Yeo, Y. Zhuo, B. Li, J. Seo, Y. Cao, “Improving the efficiency of CMOS image sensors through in-sensor selective attention,” IEEE International Symposium on Circuits & Systems, pp. 1-4, 2023.

G. R. Nair, H. Suh, M. M. Halappanavar, F. Liu, J. Seo, Y. Cao, “FPGA acceleration of GCN in light of the symmetry of graph adjacency matrix,” Design, Automation, and Test in Europe, pp. 1-6, 2023.

J. Sun, L. Yang, J. Zhang, F. Liu, M. Halappanavar, D. Fan, Y. Cao, “Self-supervised novelty detection for continual learning: A gradient-based approach boosted by binary classification,” pp. 118-133, in Continual Semi-Supervised Learning, Edited by F. Cuzzolin, K. Cannons, V. Lomonaco, Lecture Notes in Artificial Intelligence, Springer, 2022.

F. Zhang, L. Yang, J. Meng, J. Seo, Y. Cao, D. Fan, “XMA2: A crossbar-aware multi-task adaption framework via 2-tie mask,” Frontiers in Electronics, Integrated Circuits and VLSI, pp. 1-13, December 2022. 

G. Krishnan, Z. Wang, I. Yeo, L. Yang, J. Meng, M. Liehr, R. Joshi, N. C. Cady, D. Fan, J. Seo, Y. Cao, “Hybrid RRAM/SRAM in-memory computing for robust DNN acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 41, no. 11, pp. 4241-4252, November 2022. 

X. Du, S. K. Venkataramanaiah, Z. Li, H.-S. Suh, S. Yin, G. Krishnan, F. Liu, J. Seo, Y. Cao, “Efficient continual learning at the edge with progressive segmented training,” Neuromorphic Computing and Engineering, Focus Issue on Algorithms for Neuromorphic Computing, vol. 2, no. 4, pp. 1-12, October 2022.

G. Krishnan, L. Yang, J. Sun, J. Hazra, X. Du, M. Liehr, Z. Li, K. Beckmann, R. V. Joshi, N. C. Cady, D. Fan, Y, Cao, “Exploring model stability of deep neural networks for reliable RRAM-based in-memory acceleration,” IEEE Transactions on Computers, vol. 71, no. 11, pp. 2740-2752, November 2022.

S. Mandal, G. Krishnan, A. A. Goksoy, G. Nair, Y. Cao, U. Ogras, “COIN: Communication-aware in-memory acceleration for graph convolutional networks,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 12, no. 2, pp. 472-485, June 2022.

G. Krishnan, S. K. Mandal, C. Chakrabarti, J. Seo, U. Y. Ogras, Y. Cao, “Impact of on-chip interconnect on in-memory acceleration of deep neural networks,” ACM Journal on Emerging Technologies in Computing Systems, Special Issue on Computation-In-Memory, vol. 18, no. 2, pp. 1-22, April 2022

Z. Wang, G. R. Nair, G. Krishnan, S. K. Mandal, N. Cherian, J. Seo, C. Chakrabarti, U. Y. Ogras, Y. Cao, “AI computing in light of 2.5D interconnect roadmap: Big-little chiplets for in-memory acceleration,” International Electron Devices Meeting, pp. 23.6.1-23.6.4, 2022.

G. Krishnan, A. Alper Goksoy, S. K. Mandal, Z. Wang, C. Chakrabarti, J. Seo, U. Ogras, Y. Cao, “Big-little chiplets for in-memory acceleration of DNNs: A scalable heterogeneous architecture,” International Conference on Computer Aided Design, pp. 1-9, 2022.

A. Hasssan, J. Li, Y. Cao, J. Seo, “Spatial-temporal data compression of dynamic vision sensor output with high pixel-level saliency using low-precision sparse autoencoder,” Annual Asilomar Conference on Signals, Systems, and Computers, pp. 344-348, 2022.

G. Krishnan, Z. Wang, L. Yang, I. Yeo, J. Meng, R. Joshi, N. C. Cady, D. Fan, J. Seo, Y. Cao, “Hybrid IMC architecture for robust DNN acceleration,” International Conference on Solid State and Integrated Circuit Technology, pp. 1-4, 2022. 

A. D. Gaidhane, Z. Yao, Y. Cao, “Graph-based compact modeling (GCM) of CMOS transistors for efficient parameter extraction: A machine learning approach,” International Conference on Simulation of Semiconductor Processes and Devices, pp. 1-2, 2022.

G. Krishnan, Z. Wang, I. Yeo, L. Yang, J. Meng, M. Liehr, R. Joshi, N. C. Cady, D. Fan, J. Seo, Y. Cao, “Hybrid RRAM/SRAM in-memory computing for robust DNN acceleration,” International Conference on Compilers, Architectures, and Synthesis for Embedded Systems, pp. 1-12, 2022.

F. Zhang, L. Yang, J. Meng, J. Seo, Y. Cao, D. Fan, “XMA: A crossbar-aware multi-task adaption framework via shift-based mask learning method,” Design Automation Conference, pp. 271-276, 2022.

G. Krishnan, S. K. Manda., C. Chakrabarti, J. Seo, U. Y. Ogras, Y. Cao, “Heterogeneous chiplet-based architecture for in-memory acceleration of DNNs,” HiPChips Chiplet Workshop, International Symposium on Computer Architecture, 2022. 

F. Zhang, L. Yang, J. Meng, Y. Cao, J. Seo, D. Fan, “XST: A crossbar column-wise sparse training for efficient continual learning,” Design, Automation, and Test in Europe, pp. 48-51, 2022. [best IP award]

B. H. Smith, J. Harrison, Y. Cao, T. Pavlic, M. Bazhenov, “Energy-efficient neuromorphic computing in light of the structural and functional evolution of multi-scale insect brains,” Energy Consequences of Information Workshop, 2022.

J. Sun, L. Yang, J. Zhang, F. Liu, M. M. Halappanavar, D. Fan, Y. Cao, “Gradient-based novelty detection boosted by self-supervised binary classification,” The Association for the Advancement of Artificial Intelligence (AAAI) Conference on Artificial Intelligence, pp. 8370-8377, 2022.

F. Zhang, J. Meng, L. Yang, Y. Cao, J. Seo, D. Fan, “XBM: A crossbar column-wise binary mask learning method for efficient multiple task adaption,” Asia and South Pacific Design Automation Conference, pp. 610-615, 2022.

R. Saligram, W. Chakraborty, N. Cao, Y. Cao, S. Datta, A. Raychowdhury, “Power-performance analysis of digital standard cells in 28nm bulk CMOS at cryogenic temperature using BSIM models,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 7, no. 2, pp. 193-200, December 2021.

G. Krishnan, S. Mandal, M. Pannala, C. Chakrabarti, J. Seo, U. Ogras, Y. Cao, “SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks,” ACM Transactions on Embedded Computing Systems, vol. 20, no. 5s, pp. 1-24, October 2021.

X. Du, B. Bhushanam, J. Yu, D. Choudhary, E. Gao, L. Feng, J. Park, Y. Cao, A. Kejariwal, “Alternate model growth and pruning for efficient training of recommendation systems,” International Conference on Machine Learning and Applications, pp. 1417-1424, 2021.

H. Suh, J. Meng, T. Nguyen, S. K. Venkataramanaiah, V. Kumar, Y. Cao, J. Seo, “Algorithm-hardware co-optimization for energy-efficient drone detection on resource-constrained FPGA,” International Conference on Field Programmable Technology, pp. 1-9, 2021.

G. Krishnan, L. Yang, J. Sun, J. Hazra, X. Du, M. Liehr, K. Beckmann, R. V. Joshi, N. C. Cady, D. Fan, Y. Cao, “Robust RRAM-based in-memory computing in light of model stability,” Materials Research Society Fall Meeting & Exhibit, Symposium SB04, Materials and Algorithms for Neuromorphic Computing and Adaptive Bio-Interfacing, Sensing and Actuation, SB04.09.03, 2021. 

G. Krishnan, S. Mandal, M. Pannala, C. Chakrabarti, J. Seo, U. Ogras, Y. Cao, “System-level benchmarking of chiplet-based IMC architectures for deep neural network acceleration,” International Conference on ASIC, pp. 41-44, 2021. 

J. Sun, L. Yang, J. Zhang, F. Liu, M. M. Halappanavar, D. Fan, Y. Cao, “Self-supervised novelty detection for continual learning: A gradient-based approach boosted by binary classification,” International Joint Conference on Artificial Intelligence, the First International Workshop on Continual Semi-Supervised Learning, 2021.

S. Joshi, S. Haney, Z. Wang, F. Locatelli, Y. Cao, B. Smith, M. Bazhenov, “Learning in the inhibitory network of the honeybee antennal lobe,” Annual Computational Neuroscience Meeting, P183, 2021.

F. Liu, M. Halappanavar, Y. Cao, P. Li, D. Womble, “Data-driven framework for decision and control of dynamic systems,” Society for Industrial and Applied Mathematics (SIAM) Annual Meeting, MS78, Data-Driven Decision Control for Complex Systems, 2021.

G. Krishnan, S. Mandal, M. Pannala, C. Chakrabarti, J. Seo, U. Ogras, Y. Cao, “SIAM: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks,” International Conference on Hardware/Software Codesign and System Synthesis, pp. 1-24, 2021.

A. Nolastname, M. A. A. Ibrahim, A. M. Boutros, M. Hall, A. Kuzhively, A. Mohanty, E. Nurvitadhi, V. Betz, Y. Cao, J. Seo, “End-to-end FPGA-based object detection using pipelined CNN and non-maximum suppression,” International Conference on Field-Programmable Logic and Applications, pp. 76-82, 2021.

X. Du, Z. Li, F. Liu, Y. Cao, “Evolutionary NAS in light of model stability for accurate continual learning,” International Joint Conference on Neural Networks, pp. 1-8, 2021.

G. Krishnan, S. K. Mandal, C. Chakrabarti, J. Seo, U. Y. Ogras, Y. Cao, “Interconnect-centric benchmarking of in-memory acceleration for DNNs,” China Semiconductor Technology International Conference, pp. 1-4, 2021. 

G. Krishnan, J. Sun, J. Hazra, X. Du, M. Liehr, Z. Li, K. Beckmann, R. V. Joshi, N. C. Cady, Y. Cao, “Robust RRAM-based in-memory computing in light of model stability,” International Reliability Physics Symposium, pp. 1-5, 2021.

Y. Ma, G. Krishnan, Y. Cao, L. Ye, R. Huang, “SWIFT: Small-world-based structural pruning to accelerate DNN inference on FPGA,” ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 148, 2021.

G. Krishnan, J. Hazra, M. Liehr, X. Du, K. Beckmann, R. V. Joshi, N. C. Cady, Y. Cao, “Design limits of in-memory computing: Beyond the crossbar,” IEEE Electron Devices Technology & Manufacturing Conference, pp. 292-294, 2021.

G. Krishnan, S. K. Mandal, C. Chakrabarti, J. Seo, U. Y. Ogras, Y. Cao, “Interconnect-aware area and energy optimization for in-memory acceleration of DNNs,” IEEE Design & Test of Computers, vol. 37, no. 6, pp. 79-87, December 2020.

S. K. Mandal, G. Krishnan, C. Chakrabarti, J. Seo, Y. Cao, U. Y. Ogras, “A latency-optimized reconfigurable NoC for in-memory acceleration of DNNs,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 10, no. 3, pp. 362-375, September 2020.

G. Charan, A. Mohanty, X. Du, G. Krishnan, R. V. Joshi, Y. Cao, “Accurate inference with inaccurate RRAM devices: A joint algorithm-design solution,” IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 6, no. 1, pp. 27-35, June 2020.  

Y. Ma, Y. Cao, S. Vrudhula, J. Seo, “Performance modeling for CNN inference accelerators on FPGA,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 4, pp. 843-856, April 2020.

Y. Ma, Y. Cao, S. Vrudhula, J. Seo, “Automatic compilation of diverse CNNs onto high-performance FPGA accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 2, pp. 424-437, February 2020.

Z. Li, X. Du, Y. Cao, “DAT-RNN: Trajectory prediction with diverse attention,” International Conference on Machine Learning and Applications, pp. 1512-1518, 2020.

S. K. Venkataramanaiah, S. Yin, Y. Cao, J. Seo, “Deep neural network training accelerator designs in ASIC and FPGA,” International SoC Design Conference, pp. 21-22, 2020. 

S. K. Venkataramanaiah, H. Suh, E. Nurvithadhi, A. Dasu, Y. Cao, and J. Seo, “FPGA-based low-batch training accelerator for modern CNNs featuring high bandwidth memory,” International Conference on Computer Aided Design, pp. 1-8, 2020.

G. Krishnan, Y. Ma, Y. Cao, “Small-world-based structural pruning for efficient FPGA inference of deep neural networks,” International Conference on Solid-State and Integrated Circuit Technology, pp. 1-5, 2020. 

Z. Zhu, H. Sun, K. Qiu, L. Xia, G. Krishnan, G. Dai, D. Niu, X. Chen, X. S. Hu, Y. Cao, Y. Xie, Y. Wang, H. Yang, “MNSIM 2.0: A behavior-level modeling tool for memristor-based neuromorphic computing systems,” Great Lakes Symposium on VLSI, pp. 1-6, 2020.

S. K. Vendataramanaiah, X. Du, Z. Li, Y. Cao, J. Seo, “Efficient and modularized training on FPGA for real-time applications,” International Joint Conference on Artificial Intelligence, Demonstrations Track, pp. 5237-5239, 2020.

X. Du, Z. Li, J. Seo, F. Liu, Y. Cao, “Noise-based selection of robust inherited model for accurate continual learning,” IEEE Conference on Computer Vision and Pattern Recognition, Workshop on Continual Learning, pp. 1-6, 2020.

X. Du, S. K. Vendataramanaiah, Z. Li, J. Seo, F. Liu, Y. Cao, “Online knowledge acquisition with selective inherited model,” International Joint Conference on Neural Networks, pp. 20210.1-7, 2020.

L. Yang, Z. He, Y. Cao, D. Fan, “Non-uniform DNN structured subnets sampling for dynamic inference,” Design Automation Conference, pp. 1-6, 2020.

G. Charan, J. Hazra, K. Beckmann, X. Du, G. Krishnan, R. V. Joshi, N. C. Cady, Y. Cao, “Accurate inference with inaccurate RRAM devices: Statistical data, model transfer, and on-line adaptation,” Design Automation Conference, pp. 1-6, 2020.

G. Krishnan, S. K. Mandal, C. Chakrabarti, J. Seo, U. Y. Ogras and Y. Cao, “Impact of on-chip interconnect on in-memory acceleration of deep neural networks,” Design, Automation & Test in Europe, Computation In-Memory: from Device to Applications Workshop (CIMW), pp. 1-6, 2020.

Z. Li, Y. Cao, “GAR: Graph assisted reasoning for object detection,” The Winter Conference on Applications of Computer Vision, pp. 1295-1304, 2020.